1. Field of the Invention
This invention pertains to multifrequency tone receivers as used in telecommunication systems and more particularly to an improved parity checking circuit for use with tone receivers.
2. Description of the prior Art
Multifrequency signaling in telephone systems has become quite common because of the advantages provided over interrupted direct current signaling. The principle advantage of this type of system is the speed and accuracy with which a subscriber may operate a pushbutton telephone subset. In such systems multifrequency signal bursts each indicative of a digit are generated at a telphone substation and received by a signal receiver. This signal receiver separates the component frequencies of the signal bursts and indicates their presence to register apparatus. The signal receiver also includes apparatus for timing a minimum signal duration before allowing signals to be registered. This prevents a false indication of a digit due to other voice frequency signals in the transmission network (including noise). At the end of the predetermined time interval the signal detecting apparatus is operated to provide an output to the register.
To guard against false outputs one method of tone decoding requires the presence of two valid tones for a certain minimum duration. The presence of such two valid tones is commonly called parity and a parity timer insures that the two tones are present for the required time.
In such multifrequency signaling systems it is common to utilize eight tones divided into two groups of four tones each. The low group is made up of the four lower tones and the high group made up of the four higher tones. A valid tone pair then is made up of one tone from each group. In many existing multifrequency receivers, the low group detector outputs are combined through an OR gate and the high group detector outputs are also combined through a different OR gate. These signals indicating that a detector in their group is on, are then fed into a common AND gate. A true output from the AND gate indicates that a tone from each group is present and a parity condition exists. Examples of this form of parity detection are found in U.S. Pat. No. 3,140,357 to W. Bischof et al and U.S. Pat. No. 3,288,940 to G. H. Bennett et al.
Another form of tone detector exemplified by U.S. Pat. No. 3,128,349 to F. P. Boesch et al teaches that once a tone is detected in either high or low group all other tones are inhibited for the duration of the timing period established by an associated timer. In this manner if a false signal is followed immediately by a valid signal, the valid signal may be missed.
In circuits like those described above, no means are present for insuring that the two tones being timed at the end of parity are the same two that initiated operation of the parity timer. For example if both high and low group detectors give outputs, the parity timer is started. If during parity timing the high group detector for one tone, turns off and the high group detector for a second high group tone turns on before an interdigital pause is recognized, parity timing will continue and valid parity detection will be made, even though the same two tones were not present for the required time. Circuitry to insure that the same two tones (one in each group) are present for the entire parity timing period is disclosed in U.S. Pat. No. 3,916,115 to L. A. Tarr. Tarr discloses a DTMF receiver containing circuits with eight detector outputs -- one detector output for each of the eight standard touch calling frequencies. He further discloses a circuit in which each detector in a given group is associated with a flip-flop which is set when a detector turns on. The setting of a flip-flop resets the other flip-flops in that group and resets a parity timer. The parity timer reset is accomplished by an R-C differentiator on the output of each flip-flop connecting to a single gate which produces a reset pulse when a flip-flop is set. A validity or parity lead indicates whether one detector from each group is on or not.
There are two problems with this approach to the problem -- both relating to difficulties in large scale integrated circuit (LSI) implementation. The first is that there is a separate output lead for each detector. If it is necessary to have the parity timer on a different LSI chip from the detector, this results in an excessive number of input and output pins. Secondly, an RC differentiator does not lend itself to LSI implementation and the function must be performed by another device. In addition, the analog parity timer must be implemented by digital means on an LSI chip.